EDN

Test engineers must join ASIC flow early

Paul Taubman is a senior design engineer for Tality Corp., Cadence Design Systems' services organization. In this article he shows how test engineers should interact with designers in order to ...
EDN

Magma creates structured ASIC flow for ChipX

SAN JOSE, Calif. — Magma Design Automation Inc. and structured ASIC vendor ChipX Corp. have put together a unified RTL-to-GDSII design flow based on Magma's Blast Create and Blast Fusion for designers ...
Semiconductor Engineering

Power Methodology For Estimation And Optimization In The ASIC/SoC Flow

In this white paper, we’ll review the many steps of today’s common ASIC/SoC power methodologies and tool flows. We’ll then propose ways you can further optimize your power methodology to more quickly ...
Electronic Design

7-nm ASIC Technology Sets Sights on Future Data Centers

7-nm ASIC technology benefits in the semiconductor industry. Role of the 7-nm ASIC advanced node in data centers. Cost trends of advanced nodes in the semiconductor industry. As more consumers embrace ...