Abstract: A 1.5-3.3 GHz, 7 mW, all-digital delay-locked loop (ADDLL) designed in a UMC 130-nm CMOS technology is presented in this paper. The proposed ADDLL uses the modified successive approximation ...
Click on code button on this page and then Download as Zip. Or better, if you use a Git app (like GitHub one), you can take advantage of the sync function to get updates of this repo easily.
Some results have been hidden because they may be inaccessible to you
Show inaccessible results